1. Field of the Invention
The present invention relates to semiconductor wafer processing, particularly to the enhancement of chip yield, performance, and timing. More particularly, the present invention relates to a methodology for modifying selected devices that affect the critical timing of the chip and developing a mask for optically trimming the gate lengths of the devices within the critical path.
2. Description of Related Art
Optical Proximity Correction (OPC) is required when a different printing of a first feature occurs because a second feature is in close proximity to the first feature. The proximity of the second feature plays a role in altering the printing image of the first feature. In order to compensate for the impact coming from the closeness of other features, proximity features are adjusted in terms of their line width and length, particularly at the gate level.
Devices in a circuit's critical path need to be strengthened individually or as a subgroup in order to optimize timing. Overexposure or reactive ion etch trim of gates cannot address the need for strengthening individual devices or subgroups since the entire chip or wafer is affected by these processes. Strengthening the devices by lowering the threshold voltage is typically considered a granular remedy resulting in a threshold voltage step function with steps that are often too few and too large. Moreover, in most instances, the remedy of lowering the threshold voltages may have already been chosen, thus representing an exhausted option. Additionally, lowered threshold voltages will cause the off-state leakage current to increase dramatically. Adding an additional mask for a selective polysilicon trim (PT) would allow for only one step, and would not allow for fine tuning the design. Furthermore, a part which is printed three-sigma short would have non-critical devices contributing substantially to the quiescent power supply current or standby current (Iddq) of the device under test. FIG. 1 depicts a graph of measured standby current (Iddq) data versus ring oscillator speed. As depicted in quadrant A, the higher the Iddq, the faster the ring oscillator speed. Quadrant C shows the opposite result: the lower the Iddq, the slower the ring oscillator.
In order to obtain higher performance and faster integrated circuit chip speeds, the gates are generally given a higher lithographic dose enabling them to be printed with a shorter gate length in terms of power flow. The gate length is commonly referred to as L-poly. In order to obtain a short gate length or short L-poly, the lithographic dose is increased in a non-isolated manner, making all gate lengths short, and yielding faster speeds for all chips simultaneously. However, in this scenario, the active or ON currents increase linearly with the shorter gate length, while the passive or OFF currents increase exponentially. Moreover, the switching speed of the chip continues to increase. These effects may lead to an operating situation where the chip exceeds its thermal cooling capacity.
FIG. 2 graphically depicts units meeting various specifications with respect to ring oscillator and standby current combinations. Below each horizontal line and to the left of each vertical line are units that meet predetermined specifications. The units that are either too slow or have too much leakage current are those above the horizontal lines and/or to the right of the vertical lines. These devices have a standby current that is unacceptably high, and may represent a majority of the yield. The higher the standby current, the more likely the devices will exceed their thermal cooling capacity.
In U.S. Pat. No. 6,205,570 issued to Yamashita on Mar. 20, 2002, entitled “METHOD FOR DESIGNING LSI CIRCUIT PATTERN”, an LSI circuit pattern that connects gates on an LSI chip is designed by estimating a chip area and the number of gates required for achieving a desired function, and determining the proper interconnect length of each of the gates. A wiring pattern is devised from these estimations. Importantly, Yamashita teaches a methodology for deriving the length of an interconnect line between gates, for example, a BEOL metallization between a first gate and a second gate. Yamashita does not derive a reduction for individual gate length within a gate.
Consequently, rather than increasing the lithographic dosage, which prints all gates short and presents a high standby current (Iddq), there is a need in the art to provide a technique for printing only selective circuits and individual gates short, so that the standby current remains at an acceptable level. In the present invention, optical proximity correction is used as a method for designing integrated circuits, and to intentionally modify the gate length of specific devices for performance enhancement reasons, or to intentionally modify the line width of a metallization wire for RC reduction purposes, or both. This is done in addition to the conventional correction of optical proximity effects.